1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, it relates to a dynamic random access memory (DRAM) refresh operation that does not depend upon a certain number of read accesses and that also does not interfere with data accesses initiated by the controller.
2. Description of the Related Art
In a dynamic random access memory (“DRAM”), data is stored as a logic one or zero by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as charge on the capacitor, the charge gradually leaks off and the data is corrupted. The time within which a refresh must be performed lest the data might be in danger of being lost is commonly referred to as the refresh interval. Therefore, a “refresh” cycle must be performed to maintain the integrity of the data. To refresh data in a memory array, the array is typically placed in a read mode to obtain the present data stored in a row of memory cells. Subsequently, this data is used as new input data that is re-written into the row of memory cells, thus maintaining the stored data. An important aspect of the refresh cycle of prior art DRAMs is that no other operation involving a different row in the array can occur simultaneously during the refresh operation.
A functional block diagram of a typical 64M SDRAM is shown in FIG. 1. Since SDRAM operation is well known in the art, only a brief description of the FIG. 1 DRAM will be provided herein. The FIG. 1 SDRAM is a quad-bank (“x16”) SDRAM having four 16, 777, 216-bit banks 10A–10D organized as 4,096 rows by 256 columns by 16 bits. Circuit blocks 12A–12D include sense amplifiers coupled to each column within the memory array to transform charge on the capacitor in the memory cell into a valid logic one or zero. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Address bits registered coincident with an ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
In the DRAM of FIG. 1, two types of refresh cycles are available; auto refresh and self-refresh. The self-refresh cycle automatically and internally refreshes the data sequentially in the memory arrays. The auto refresh cycle is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. Providing a distributed AUTO REFRESH command every 15.625 μs will meet the refresh requirement and ensure that each row is refreshed. The SELF REFRESH command can be used to retain data in the SDRAM even if the rest of the system is powered down. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles.
One problem associated with such refresh cycles is that a given refresh cycle may conflict with a controller-generated access command (e.g., a read or write command). Many DRAM's are configured for deterministic latency which means that an access can never lose priority; and therefore, the refresh operation must wait (e.g., put into a queue) until the access has been completed. The danger with such a practice, of course, is that a refresh operation may be postponed for a period of time greater than a predetermined refresh interval, thus placing the data at risk.
One approach to solving this problem has been proposed by Monolithic System Technology, Inc. with its 1T-SRAM technology. Under the 1T-SRAM approach, refresh operations are triggered by read commands. One problem with relying upon read commands to trigger a refresh operation is that it can result in refresh overkill. That is, a read command may be received from the system processor more frequently than a refresh is actually required, thus, wasting valuable power resources. Another problem with relying upon read commands is that if the memory is idle for greater than the refresh interval (e.g., 64 ms), data will be lost.
Yet another approach to the problem proposes to trigger a refresh operation off of a clock pulse (e.g., after a predetermined number of clock pulses, a refresh operation is triggered). However, under this approach, there is no way to guarantee that the refresh will not begin just before a read command. In such a case, if the read access is delayed until the refresh operation is completed, the overall time required to access memory is increased.
Another approach to the refresh problem is disclosed in U.S. Pat. No. 6,028,804 (the “'804 patent”). The '804 patent discloses a method of operating a memory array which contains memory cells requiring periodic refresh in which a refresh is performed only if no external access is determined to be pending. An accumulator is disclosed for accumulating (i.e., delaying) refresh requests that conflict with an external access for up to seven refresh requests (or 56 μs).
According to the '804 patent, external memory accesses are allowed to continue for a period of up to 56 μs without losing refresh cycles. The '804 patent states that back-to-back external accesses longer than 56 μs generally do not occur. The '804 patent also states that the memory cycle of its disclosed memory system is equal to one clock cycle. Thus, the '804 patent does not consider the special complex problems associated with having a memory cycle that is equal to multiple clock cycles, such as e.g., the fact that access commands must be disallowed for certain clock cycles. In addition, the '804 patent does not provide for simultaneous operations (e.g., read, write or refresh). Thus, there exists a need for a hidden DRAM refresh operation that does not depend upon a certain number of read accesses, that does not interfere with data accesses initiated by the controller, that allows for simultaneous operations and that is consistent with today's memory cycles which may last for multiple clock cycles.